The study is aimed to solve the problem that single cycle sampling data shows low precision for limit detector. Based on the idea of synthetic sampling method proposed by Professor Dai Xianzhong, the limit synthetic sampling method is put forward. Then the limit detector is designed based on the multi-cycle limit sample method. The limit detector includes First In First Out(FIFO) modular，register modular and compare modular. It obtains precise values in five cycles of data sampling. Through the simulation verification on the platform of QUARTUS, the design is able to detect the limit value of 3 ns offset accurately.