A novel LVTSCR structure for 5 V on-chip protection against Electrostatic Discharge(ESD) stress at input or output pads is presented. Silvaco 2D TCAD software is used to simulate the device including electrical and thermal characteristics. The new device exchanges the diffusion region of N+ and P+ in N-WELL and introduces a PMOS-like structure to discharge ESD current before Low Voltage Triggering SCR(LVTSCR) starting to work. And the device simulation results show that it obtains a higher holding voltage(10.51 V) and a faster turn on speed(1.05×10-10 s) compared with LVTSCR, with the triggering voltage only increasing slightly from 12.45 V to 15.35 V. Also, in order to make sure that the PMOS structure will trigger first and will not cause thermal breakdown problem, nearly the same channel length as NMOS should be chosen for PMOS structure.