Program architecture is designed to meet the requirements on time sequence control based on CompactRIO and LabVIEW. According to different requirements on instructions responses, the time sequence control software is divided into two layers:Field Programmable Gate Array(FPGA) layer and Real Time(RT) layer. Data communication is achieved by using Direct Memory Access First-In First-Out(DMA FIFO) and interface widget between the two layers. Function of time sequence control and hardware logical operations are achieved by using state machine in FPGA layer. Human-computer interaction is carried out in RT layer. The state of time sequence is passed to upper level computer. As a result of measurement, hardware operations response time is less than 50 μs.