With the scaling of Complementary Metal Oxide Semiconductor(CMOS) process，Multi-Processor System-on-Chip(MPSoC) is becoming a preferable way to improve the rate of data processing. Because Network-on-Chip(NoC) is the key part of MPSoC，acting as the communication medium, the design of NoC would influence the performance of the whole system. Two different NoCs are studied and the influence of router structure on MPSoC is discussed. Experimental results obtained through ModelSim simulation show that the transmission latency of the router with delay optimization techniques has decreased by 6 times. Besides，the MPSoC on Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuits(ASIC) are implemented respectively. The areas and critical delay gap between them through two corresponding synthesis Computer Aided Design(CAD) flows in 0.13 μm process are measured. The area of FPGA is roughly 29 to 33 times that of ASIC, and the critical delay of FPGA is 4.5 to 7.5 times that of ASIC.