A Memorized Field Programmable Gate Array(FPGA) Configuration Model Search(MCMS) algorithm is presented to automatically generate configuration bitstream of routing resources to solve the bitstream configuration problem commonly existing in Static Random Access Memory(SRAM) FPGA. The main objective is to reduce the time for generating configuration bitstream of routing resources and improve the correctness of configuration process. This is achieved by allowing the MCMS algorithm to extract the model of configuration bitstream from the behavioral Verilog HDL(Hardware Design Language) netlist that describes the FPGA architecture, utilizing the model to automatically generate the bitstream of routing resource on the routing path based on the routing result. Our experimental results using a homogeneous SRAM FPGA with 30 million gates that contains 30 million configuration bits have shown a 298 times improvement in time efficiency, from 6 days when manually extracting the configuration bitstream model to 29 minutes when using MCMS to complete the extraction. For a heterogeneous FPGA of the same scale, it takes one week for the manual method to extract the configuration bitstream model, while the MCMS only needs 26 minutes, which improves the time efficiency by 394 times. By using the automatic method, not only the time for generating configuration bitstream can be shortened, but also the correctness of configuration bitstream generated can be ensured. As a general configuration bitstream model extracting procedure, the proposed approach is applicable for homogeneous and heterogeneous FPGAs.