A 12 bit 60 MS/s pipeline Analog-to-Digital Conversion(ADC) is introduced. Using the sample and hold circuit，the continuous variation of the analog signal is sampled by a certain time interval，in order to achieve accurate signal. Gain bootstrap amplifier is adopted to improve the establishment of signal linearity. The pipeline structure of 1.5 bit per stage is utilized to achieve redundancy encoding，and reduce the offset voltage of the comparator. A new pre-amplifier comparator structure which can eliminate the static power is put forward. The design of schematic and layout is based on Huali Microelectronics Corp(HMC) 55 nm Complementary Metal Oxide Semiconductor(CMOS) technology. Fast Fourier Transform(FFT) analysis results on post simulation give the Dynamic parameters: Spurious Free Dynamic Range(SFDR) of 86.18 dB，Signal-to-Noise Ratio(SNR) of 72.91 dB，Signal-to-Noise-and-Distortion Ratio(SNDR) of 72.8 dB，Effective Number of Bits(ENOB) of 11.72 bit.