The width of Single-Event Transient(SET) pulse is one of the most important parameters for evaluating soft-error rate in electronic systems. Analytical calculation is performed in 0.13 μm Partially Depleted Silicon On Insulator(PDSOI) Complementary Metal Oxide Semiconductor(CMOS) logic. Simulation in inverter chain is carried out to study the variation of critical pulse width and transmission rate. Results reveal that SET pulse width changes from dozens of picosecond to hundreds of picosecond in duration; meanwhile, the stage of inverter chain has a great influence on critical pulse width and transmission rate. Finally，derived by simulation of D Flip-Flop(DFF)，the set-up time and hold time are related to the input pulse width when pulse width is short. The results are helpful for improving the accuracy of electrical masking model and latch masking model.