Programmable logic, which mainly consists of LUTs and registers, is a central part of Field Programmable Gate Array(FPGA) architecture. Exploring the structure of the programmable logic is important in FPGA’s research. Fracturable logic can bring flexibility during circuit implementation. In this paper, the influences of fracturable factor on the performance of circuit are studied from the point of view of fracturable logic based on 6-LUT. Simulation experiment is based on open-source FPGA CAD tools－ABC and VPR, and the circuits are from VPR benchmarks. The performance is evaluated from three aspects: area, delay and area-delay product. The experiment results show that: a) the fracturable factor does not make much influence on critical path delay; b) discussing from the aspects of area and area-delay product, the circuit will perform better when assigning the value of fracturable factor to 2.