A CMOS programmable gain Low Noise Amplifier(LNA) is implemented for analog bus receiver applications. There are high/medium/low gain channels, which are applied to meet noise, linearity and input impedance and other performance requirements in analog bus reception in condition of different input signal amplitude. The technique is adopted to compensate the input leakage current of LNA via a capacitor, which yields a real-time high-input impedance. The bandwidth-extension loads is adopted to reduce the phase shift, which solves the current compensating faulty because of the phase shift. An improvement of linearity in medium/low gain channels is achieved by applying Differential Multiple Gated Transistor(DMGTR) and negative feedback technique. The amplifier is designed using 0.18 μm CMOS technology. The simulation result exhibits a gain of -14.3 dB to -25 dB, an input impedance higher than 2.4 kΩ, an -1.6 dBm Input Third-order Intercept Point(IIP3)(maximum 20.7 dBm), an input-referred noise voltage of 1.79 nV·Hz-1/2@1 MHz-0.87 nV·Hz-1/2@33 MHz in the 25 dB gain mode and an power consumption of 6.5 mA at 1.8 V at frequencies from 1 MHz to 33 MHz.