Two-step dry etch method in the Inductive Coupled Plasma(ICP) chamber is proposed and applied to the SiN gate foot definition during the self-aligned 0.5 micron T-gate fabrication for GaN High Electron Mobility Transistor(GaN HEMT). The main etching part forms a tilted silicon nitride side wall, which reduces the electric field intensity in the channel under the gate and improves the gate metal filling in the silicon nitride recess. The soft landing part performs the over-etching process with a very low bias power to ensure the complete removal of silicon nitride and reduce the channel damage. Compared with the control device without any optimization, the off-state breakdown voltage of the optimized device shows an obvious increase from 140 V to more than 200 V. Moreover, the output power density and the Power Added Efficiency(PAE) at 3.5 GHz are promoted from 5.8 W/mm to 8.7 W/mm and 55.5% to 66.7%, respectively. After un-biased highly accelerated stress test for 96 hours, no obvious change in the appearance of the optimized device can be observed, and the change of the maximum drain current is less than 5%, indicating that the device reliability is pretty good.