Physical Unclonable Function(PUF) is a highly practical hardware security primitive that can be widely used in information security fields such as IoT device authentication. However, the strong PUF has strong correlation between inputs and outputs, which makes it vulnerable to attacks by Machine Learning(ML) algorithms. In view of this, a delay-controllable dual-edge Arbiter PUF(APUF) circuit based on the delay-controllable unit and dual-edge triggering mechanism is proposed. Firstly, a delay- controllable switching circuit is employed to optimize the path of the conventional APUF and adjust the circuit delay deviation to reduce the correlation between the Challenge-Response Pair(CRP). Secondly, a rising-edge arbiter and a falling-edge arbiter are employed to capture the dual-edge delay response of the PUF circuit respectively, which double increases the number of pairs of CRP of the PUF. Finally, a dual-edge arbiter PUF circuit is proposed based on the TSMC 65 nm CMOS process and the Cadence Virtuoso design platform, the circuit and layout are realized in a fully customized way. The experimental results show that the logic function of the circuit is correct, the uniqueness and reliability of the PUF are 51.01% and 0.025 57 respectively. And the prediction rates of ML attacks corresponding to Logistic Regression(LR), Support Vector Machine(SVM), Artificial Neural Network(ANN) and Light Gradient Boosting Machine(Light GBM) algorithms are 59.71%, 62.75%, 86.00% and 80.92%, the resistance to ML attack is significantly improved.