In order to satisfy the encryption requirements of radar system data transfer, the Counter (CTR) mode of Advanced Encryption Standard(AES) was modified into a stream cipher. Through structure folding and module reuse, the resource utilization was reduced and the throughput was increased. In Spartan3 FPGA, 276.53 Mbps throughput could be achieved only by using 728 slices. The resource-saving pure logic mode and high-speed distributed memory mode were implemented in the design. On-the-fly key scheduling and pipeline were also performed, which led to high throughput and security level. The real-life test showed the design had satisfied the requirements of radar signal encryption, which revealed a great potential of stream mode AES in radar signal transmission.