Along with large scale integrated circuit development，interconnect delay has become the bottleneck of restricting its performance. Buffer insertion is one of the ways to solve interconnect delay problem. VG algorithm is the classical algorithm of buffer insertion interconnection sequence optimization. The improvement is performed based on the three main operation processes of VG algorithm in this paper. Red-black tree data structure is employed to store and route topology data structure，therefore speed up the update and access of the data structure；fast redundancy discrimination and sorting method are adopted to decrease the quantity and the complexity of the optimal solution. The circuits included in standard test circuit International Symposium of Circuits and Systems in 1989 (ISCAS89) set are used to test the proposed method，and the test results show that although the running time of both the improved method and the traditional method is linearly increasing with the increasing of circuit scale, the advantages of the improved algorithm are still more obvious than traditional method. Meanwhile，the advantages are also more significant along with the buffer numbers increasing in the buffer library. In the case of one buffer in the buffer library，the running time of improved algorithm is 73.28% of VG algorithm, while in the case of 8 buffers and 20 buffers in the buffer library, the running time of improved algorithm is 67.34% and 63.05% of VG，respectively. The proposed method can effectively reduce buffer insertion time in the mass interconnection sequence optimization.