Single Carrier-Frequency Domain Equalization(SC-FDE) is effective to overcome multipath fading in digital communication and it is widely used for its performance. SC-FDE is adopted in broadband communication systems and a symbol transmission rate of 27.5 Mbps is realized under the carrier frequency of 137.5 MHz. The concatenated channel error correction coding of 1/2 rate convolution code combined with (239,223) Reed-Solomon(RS) code is used in order to improve the reliability of the system. The SC-FDE system is designed, and the key technologies of this system are analyzed. It is implemented on Field Programmable Gate Array(FPGA) hardware platform. The commissioning and validation are performed as well. The actual Bit Error Ratio(BER) test of the system is executed.