The load model and the index requirements are proposed through analyzing the working process of reference buffer in pipelined Analog to Digital Converter(ADC) in the paper. Finally a reference buffer used in high-speed high-precision pipelined ADC is designed. The buffer adopts an improved open loop structure to induce design complexity，power consumption and area. Moreover an enhanced source follower structure is used to improve driving capability and stability. The design of schematic and layout is based on Huali Microelectronics Corporation(HMLC) 55 nm Complementary Metal-Oxide-Semiconductor(CMOS) technology，and layout area is 280 μm×240 μm. The post simulation result shows that the power of buffer is 3mA and the setting time is 4.3 ns. The buffer can be used in 60 MS/s 12 bit pipelined ADC.