Abstract:An embedded Field-Programmable Gate Arrays(FPGA) Digital Signal Processor(DSP) core's architecture which supports efficient width variable addition is presented. Compared with the Stratix-III DSP core of Altera corporation, the optimized architecture will give higher efficiency to a variety of applications such as addition, multiply-addition and accumulation. It can not only reduce the circuit area but also improve the circuit performance by using software to pre-process the data with different types and bit-width. Meanwhile, a multiply-bypass circuit and two-stage sign extensional addition circuit are added to the DSP core, which implements a high bit-width, high-speed pipelined operation and reduces the circuit area as well. The design of DSP IP(Intellectual Property) core utilizes TSMC 55 nm CMOS technology, which supports nine-operation modes including 72 bit addition and 36 bit multiplication for variable width inputs.