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适用于FPGA的浮点型DSP硬核结构设计
A suitable design of floating-point DSP hard core structure in FPGA
投稿时间:2017-11-27  修订日期:2018-01-24
中文关键词:现场可编程门阵列  数字信号处理器  硬核结构  浮点数运算
英文关键词:Field-Programmable Gate Array(FPGA)  Digital Signal Processor(DSP)  hardcore structure  floating point
基金项目:国家自然科学基金资助项目(61876172,61704173);北京工商大学食品安全大数据技术北京市重点实验室开放课题基金资助项目(BKBD-2017KF05);北京工商大学食品安全大数据技术北京市重点实验室开放课题基金资助项目(BKBD-2017KF05) ;北京市科技重大专项课题(Z171100000117019)
作者单位
赵 赫 1.Institute of ElectronicsChinese Academy of SciencesBeijing 100190China2.School of MicroelectronicsUniversity of Chinese Academy of SciencesBeijing 100049China 
黄志洪 Institute of ElectronicsChinese Academy of SciencesBeijing 100190China 
余 乐 Beijing Key Laboratory of Big Data Technology for Food SafetyBeijing Technology and Business UniversityBeijing 100048China 
杨海钢 1.Institute of ElectronicsChinese Academy of SciencesBeijing 100190China2.School of MicroelectronicsUniversity of Chinese Academy of SciencesBeijing 100049China 
许仕龙 The 54th Research InstituteChina Electronics Technology Group CorporationShijiazhuang Hebei 050081China 
郝亚男 The 54th Research InstituteChina Electronics Technology Group CorporationShijiazhuang Hebei 050081China 
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中文摘要:
      提出一种浮点型数字信号处理器(DSP)硬核结构,在兼容定点数运算的同时,也为浮点数运算提供较好支持。目前各大现场可编程门阵列(FPGA)主流厂商在实现浮点数运算功能时均采用软核实现方式,即将浮点数运算算法映射到芯片上,通过逻辑资源和DSP模块实现。相比于传统方法,提出的硬核结构在不占用FPGA中其他逻辑资源情况下,仅利用DSP模块便能完成浮点数运算。设计中,充分考虑负载和时延影响,插入多级流水线,显著提高浮点数的计算效率。采用中芯国际(MCI)28 nm工艺设计并完成所提出的浮点型DSP硬核结构。仿真结果表明,所提出的硬核结构的单个浮点数加法和乘法效率为0.4 Gflops。
英文摘要:
      A floating-point Digital Signal Processor(DSP) hardcore structure is proposed. The hardcore structure not only is compatible with fixed-point operation, but also provides better support for floating-point operation. At present, the major manufacturers of Field-Programmable Gate Array(FPGA) use soft core to implement floating-point arithmetic, which maps floating-point arithmetic to the chip and realizes it through logical resources and DSP module. Compared with traditional methods, the proposed hard-core architecture can complete floating-point arithmetic only by using DSP module without occupying other logic resources in the FPGA. At the same time, in the design process of the DSP, the influence of load and time delay is fully considered, and the multi-level pipeline is reasonably inserted, which greatly improves the calculation efficiency of floating-point number. The floating-point DSP hard-core structure is designed and completed by the Semiconductor Manufacturing International(MCI) 28 nm technology. The simulation results of the proposed hard-core structure show that the single floating-point efficiency of addition and multiplication is 0.4 Gflops.
引用本文:赵 赫,黄志洪,余 乐,杨海钢,许仕龙,郝亚男.适用于FPGA的浮点型DSP硬核结构设计[J].太赫兹科学与电子信息学报,2019,17(3):524~530
DOI:10.11805/TKYDA201903.0524
学科分类代码:
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