In order to run Fast Fourier Transform(FFT) algorithm more efficiently in embedded devices，an optimized design of twiddle factors for the small Cache was presented. The design can effectively enhance read-percent cache hits and improve processing speed. The selection principle of configuration parameters in different needs was given and the experimental results based on typical configuration parameters and target processor were discussed. It is proved that this optimized method can effectively improve processing speed with slight Signal to Noise Ratio(SNR) decrease.