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超导加速器低电平系统射频前端设计与实现
Design and implementation of the low level control system RF front-end of the superconducting accelerator
投稿时间:2014-05-19  修订日期:2014-06-09
中文关键词:射频前端  时钟分配  上下变频  低电平控制  超导加速器
英文关键词:RF front-end  clock distribution  up-down converter  low level control  superconducting accelerator
基金项目:国家重大科学仪器设备开发专项基金资助项目(2011YQ130018)
作者单位
劳成龙 1a.Graduate School1b.Institude of Applied ElectronicsChina Academy of Engineering PhysicsMianyang Sichuan 621999China 
冯立文 Institute of Heavy Ion PhysicsPeking UniversityBeijing 100871China 
王 芳 Institute of Heavy Ion PhysicsPeking UniversityBeijing 100871China 
杨兴繁 Institude of Applied ElectronicsChina Academy of Engineering PhysicsMianyang Sichuan 621999China 
鲁向阳 Institute of Heavy Ion PhysicsPeking UniversityBeijing 100871China 
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全文下载次数: 1940
中文摘要:
      设计了中物院太赫兹科研装置超导加速器低电平控制系统的射频前端部分,采用了信号源8663A与直接信号发生器板卡AD9858结合的方案,产生射频前端所需的30.72 MHz中频信号和1330.72 MHz本振信号。采用AD9510时钟板产生ADC和DAC采样所需的频率122.88 MHz和245.76 MHz,采样信号时间抖动仅为4 ps,由此引起的幅值采样误差和相位采样误差分别为±0.04%和±0.025%,符合设计要求。
英文摘要:
      The Radio Frequency(RF) front-end for the superconducting cavity of the high average power THz equipment is designed and implemented. By combining the signal source 8663A and the AD9858 Direct Digital Synthesizer(DDS), a signal with 30.72 MHz intermediate frequency and a local oscillator signal of 1 330.72 MHz are generated. The 30.72 MHz signal generated by the AD9858 is used as the reference signal of the clock board AD9510 for generating Analog to Digital Converter(ADC) and Digital to Analog Converter(DAC) driving sampling signal of 122.88 MHz and 245.76 MHz respectively. According to the measurement, the clock signal timing jitter is around 4 ps, the amplitude and phase of sampling error caused by the jitter is ±0.04% and ±0.025% respectively, which is in line with the design requirements.
引用本文:劳成龙,冯立文,王 芳,杨兴繁,鲁向阳.超导加速器低电平系统射频前端设计与实现[J].太赫兹科学与电子信息学报,2015,13(3):462~467
DOI:10.11805/TKYDA201503.0462
学科分类代码:
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