Improve SRAM SEU resistance with SOI CMOS technology
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    Abstract:

    Improving Single Event Upset(SEU) resistance of Static Random Access Memory(SRAM) is being a hotspot in the research area of electronics Radiation-Hardening. It is hard to improve the anti-SEU ability of bulk CMOS SRAMs without circuit Radiation-Hardening,whereas more area and power consumption will be spent with Radiation-Harding design. To investigate the SEU resistance of Silicon on Insulator(SOI) SRAMs,this study introduced the key technology breakthrough in SOI CMOS Radiation- Hardening process and 128 kb SRAM circuit design. The SEU experiment of a homemade 128 kb SOI SRAM showed that its threshold Linear Energy Transfer(LET) value was more than 61.8 MeV/(mg/cm2),which was higher than that of CMOS SRAMs without Radiation-Hardening design. It is concluded that SOI fabrication process is promising to obtain preferable SEU resistance of SRAMs with proper considerations on basic device and 6-T cell structure.

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ZHAO Kai, GAO Jian-tou, YANG Bo, LI Ning, YU Fang, LIU Zhong-li, XIAO Zhi-qiang, HONG Gen-shen. Improve SRAM SEU resistance with SOI CMOS technology[J]. Journal of Terahertz Science and Electronic Information,2010,8(1):91~[end].

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History
  • Received:August 17,2009
  • Revised:November 26,2009
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