Design of high-accuracy and megabit True-Time Delay chip
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The 13th Research Institute of CETC,Shijiazhuang Hebei 050051,China

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    Abstract:

    Based on the GaAs substrate Enhanced/Depletion-mode pseudomorphic High Electron Mobility Transistor(E/D pHEMT) process, a three-bit adjustable 1 400 ps Digital-Controlled Delay (DCD) chip operating in the 0.5~6 GHz frequency range has been developed. The chip measures 3.60 mm ×4.00 mm ×0.07 mm and integrates a three-bit digital-controlled delay line and a 3-bit parallel port drive circuit. Within the 0.5~6 GHz range, the DCD chip exhibits insertion loss of less than 11 dB, with insertion loss variation of less than ±0.5 dB. The Voltage Standing Wave Ratio(VSWR) for both input and output is less than 1.5 across all states. The 1 400 ps delay error can be internally adjusted to ±4 ps, achieving a delay quantity at the nanosecond level. By incorporating additional adjustable units and bonding cut-off methods, the delay accuracy is enhanced to 3‰. The chip features broadband operation, high precision, large delay quantity, and a compact size, making it well-suited for applications in antenna systems.

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陈月盈,刘帅,杨柳,赵子润.高精确度大比特位延时器芯片研制[J]. Journal of Terahertz Science and Electronic Information Technology ,2025,23(4):340~345

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History
  • Received:October 26,2024
  • Revised:December 30,2024
  • Adopted:
  • Online: May 07,2025
  • Published: