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2025, 23(4):309-316.
DOI: 10.11805/TKYDA2024224
Abstract:
To address the issue of high freewheeling losses caused by SiC Metal-Oxide-Semiconductor Field-Effect Transistors(MOSFETs) during the freewheeling process in power modules, an integrated Low-Barrier Diode SiC MOSFET(LBD-MOS) structure is proposed. The total power consumption of LBD-MOS and the conventional SiC MOSFET(CON-MOS) under the same area is investigated. Simulation results show that the freewheeling voltage drop(UF) of LBD-MOS is 1.6 V, which is 50% lower than that of CON-MOS; the switching loss (E_switch) of LBD-MOS is 187.3 μJ, which is 6% lower than that of CON-MOS. Under operating conditions with a frequency of 10 kHz and a duty cycle of 50%, the total power consumption of LBD-MOS is reduced by 22.6% compared to that of CON-MOS. LBD-MOS is suitable for applications where the freewheeling ratio is higher than 50% and the switching frequency does not exceed 1 MHz.
To address the issue of high freewheeling losses caused by SiC Metal-Oxide-Semiconductor Field-Effect Transistors(MOSFETs) during the freewheeling process in power modules, an integrated Low-Barrier Diode SiC MOSFET(LBD-MOS) structure is proposed. The total power consumption of LBD-MOS and the conventional SiC MOSFET(CON-MOS) under the same area is investigated. Simulation results show that the freewheeling voltage drop(UF) of LBD-MOS is 1.6 V, which is 50% lower than that of CON-MOS; the switching loss (E_switch) of LBD-MOS is 187.3 μJ, which is 6% lower than that of CON-MOS. Under operating conditions with a frequency of 10 kHz and a duty cycle of 50%, the total power consumption of LBD-MOS is reduced by 22.6% compared to that of CON-MOS. LBD-MOS is suitable for applications where the freewheeling ratio is higher than 50% and the switching frequency does not exceed 1 MHz.
2025, 23(4):317-321.
DOI: 10.11805/TKYDA2024223
Abstract:
The heteroepitaxial process of Gallium Nitride High Electron Mobility Transistors (GaN HEMTs) leads to the presence of a trapping effect in GaN HEMT devices. This effect causes dynamic changes in the on-resistance of the devices under continuous transient operating conditions, known as dynamic on-resistance, which is higher than the theoretical value under static conditions. This dynamic on-resistance can pose a threat to the stability of power systems. Therefore, it is necessary to investigate efficient and accurate testing methods for the dynamic on-resistance of GaN HEMT devices. The mechanism of dynamic on-resistance generation in GaN HEMT devices is introduced in this paper. In combination with practical testing requirements, a novel clamping circuit based on an ultra-high-speed voltage feedback operational amplifier is designed. The Pspice simulation tool is employed to simulate this new clamping circuit and compare it with other commonly used existing clamping circuits. The results show that this circuit can more rapidly and accurately read the drain voltage of the device after it transitions from the off-state to the on-state. It also enables the characterization of the device's on-resistance under different bias voltages and frequencies.
The heteroepitaxial process of Gallium Nitride High Electron Mobility Transistors (GaN HEMTs) leads to the presence of a trapping effect in GaN HEMT devices. This effect causes dynamic changes in the on-resistance of the devices under continuous transient operating conditions, known as dynamic on-resistance, which is higher than the theoretical value under static conditions. This dynamic on-resistance can pose a threat to the stability of power systems. Therefore, it is necessary to investigate efficient and accurate testing methods for the dynamic on-resistance of GaN HEMT devices. The mechanism of dynamic on-resistance generation in GaN HEMT devices is introduced in this paper. In combination with practical testing requirements, a novel clamping circuit based on an ultra-high-speed voltage feedback operational amplifier is designed. The Pspice simulation tool is employed to simulate this new clamping circuit and compare it with other commonly used existing clamping circuits. The results show that this circuit can more rapidly and accurately read the drain voltage of the device after it transitions from the off-state to the on-state. It also enables the characterization of the device's on-resistance under different bias voltages and frequencies.
2025, 23(4):322-330.
DOI: 10.11805/TKYDA2024403
Abstract:
In recent years, significant progress has been made in the development of domestic 6-inch SiC-based Gallium Nitride High Electron Mobility Transistors(GaN HEMTs). This paper investigates the multi-layer dielectric stress modulation technique and high-consistency backside etching technique, which are integrated into the 6-inch process. When operating at 48 V, the 0.5 μm process achieves an output power density of 8.6 W/mm at 3.5 GHz, with a power gain of 15 dB and a Power Added Efficiency(PAE) of 58.5%. When operating at 28 V, the 0.25 μm process achieves an output power density of 5.5 W/mm at 10 GHz, with a power gain of 8.7 dB and a PAE of 55.2%. The reliability of GaN devices is evaluated through High-Temperature Operating Life (HTOL) and High-Temperature Reverse Bias(HTRB) tests, with the saturation output current of the devices changing by less than 10% after 1 000 hours. The 20 W and 40 W power transistors, as well as X-band Monolithic Microwave Integrated Circuit (MMIC) power amplifiers, are fabricated to validate the process technology, with measured on-wafer yields of 90%, 86%, and 77%, respectively. The results indicate that domestic6-inch SiC-based GaN HEMTs have application potential below the Ku-band.
In recent years, significant progress has been made in the development of domestic 6-inch SiC-based Gallium Nitride High Electron Mobility Transistors(GaN HEMTs). This paper investigates the multi-layer dielectric stress modulation technique and high-consistency backside etching technique, which are integrated into the 6-inch process. When operating at 48 V, the 0.5 μm process achieves an output power density of 8.6 W/mm at 3.5 GHz, with a power gain of 15 dB and a Power Added Efficiency(PAE) of 58.5%. When operating at 28 V, the 0.25 μm process achieves an output power density of 5.5 W/mm at 10 GHz, with a power gain of 8.7 dB and a PAE of 55.2%. The reliability of GaN devices is evaluated through High-Temperature Operating Life (HTOL) and High-Temperature Reverse Bias(HTRB) tests, with the saturation output current of the devices changing by less than 10% after 1 000 hours. The 20 W and 40 W power transistors, as well as X-band Monolithic Microwave Integrated Circuit (MMIC) power amplifiers, are fabricated to validate the process technology, with measured on-wafer yields of 90%, 86%, and 77%, respectively. The results indicate that domestic6-inch SiC-based GaN HEMTs have application potential below the Ku-band.
2025, 23(4):331-339.
DOI: 10.11805/TKYDA2024517
Abstract:
The working principle of a nanosecond-level high-voltage pulse generation circuit based on a Drift Step Recovery Diode(DSRD) is introduced. The circuit is modeled, and the key circuit parameters that affect the pulse output characteristics are discussed based on the model. In the experiment, a high-voltage Silicon Carbide(SiC) DSRD device developed in the author's laboratory is employed to generate a nanosecond-level pulse voltage with a peak value of 2.27 kV and a rise time of 1.846 ns on a standard load of 50 Ω. By changing the key parameters in the circuit, the variation trends of the pulse voltage peak obtained from the tests are consistent with the analysis from the model, which validates the rationality of the model. Considering the voltage overshoot issue at the drain-source terminals of the switch during the turn-off process, a buffer capacitor is connected in parallel across the drain-source terminals. The parameters of the buffer capacitor are adjusted experimentally to reduce the overshoot voltage at the drain-source terminals without affecting the peak voltage of the DSRD pulse discharge.
The working principle of a nanosecond-level high-voltage pulse generation circuit based on a Drift Step Recovery Diode(DSRD) is introduced. The circuit is modeled, and the key circuit parameters that affect the pulse output characteristics are discussed based on the model. In the experiment, a high-voltage Silicon Carbide(SiC) DSRD device developed in the author's laboratory is employed to generate a nanosecond-level pulse voltage with a peak value of 2.27 kV and a rise time of 1.846 ns on a standard load of 50 Ω. By changing the key parameters in the circuit, the variation trends of the pulse voltage peak obtained from the tests are consistent with the analysis from the model, which validates the rationality of the model. Considering the voltage overshoot issue at the drain-source terminals of the switch during the turn-off process, a buffer capacitor is connected in parallel across the drain-source terminals. The parameters of the buffer capacitor are adjusted experimentally to reduce the overshoot voltage at the drain-source terminals without affecting the peak voltage of the DSRD pulse discharge.
2025, 23(4):340-345.
DOI: 10.11805/TKYDA2024573
Abstract:
Based on the GaAs substrate Enhanced/Depletion-mode pseudomorphic High Electron Mobility Transistor(E/D pHEMT) process, a three-bit adjustable 1 400 ps Digital-Controlled Delay (DCD) chip operating in the 0.5~6 GHz frequency range has been developed. The chip measures 3.60 mm ×4.00 mm ×0.07 mm and integrates a three-bit digital-controlled delay line and a 3-bit parallel port drive circuit. Within the 0.5~6 GHz range, the DCD chip exhibits insertion loss of less than 11 dB, with insertion loss variation of less than ±0.5 dB. The Voltage Standing Wave Ratio(VSWR) for both input and output is less than 1.5 across all states. The 1 400 ps delay error can be internally adjusted to ±4 ps, achieving a delay quantity at the nanosecond level. By incorporating additional adjustable units and bonding cut-off methods, the delay accuracy is enhanced to 3‰. The chip features broadband operation, high precision, large delay quantity, and a compact size, making it well-suited for applications in antenna systems.
Based on the GaAs substrate Enhanced/Depletion-mode pseudomorphic High Electron Mobility Transistor(E/D pHEMT) process, a three-bit adjustable 1 400 ps Digital-Controlled Delay (DCD) chip operating in the 0.5~6 GHz frequency range has been developed. The chip measures 3.60 mm ×4.00 mm ×0.07 mm and integrates a three-bit digital-controlled delay line and a 3-bit parallel port drive circuit. Within the 0.5~6 GHz range, the DCD chip exhibits insertion loss of less than 11 dB, with insertion loss variation of less than ±0.5 dB. The Voltage Standing Wave Ratio(VSWR) for both input and output is less than 1.5 across all states. The 1 400 ps delay error can be internally adjusted to ±4 ps, achieving a delay quantity at the nanosecond level. By incorporating additional adjustable units and bonding cut-off methods, the delay accuracy is enhanced to 3‰. The chip features broadband operation, high precision, large delay quantity, and a compact size, making it well-suited for applications in antenna systems.
2025, 23(4):346-352.
DOI: 10.11805/TKYDA2025005
Abstract:
A novel Avalanche Triggered MOS-Controlled Thyristor(AT-MCT) is proposed, which achieves high current peak, high current rise capability (di/dt), and non-activation protection in the non-operating state during capacitor pulse discharge. The device incorporates a highly doped N Avalanche Layer(N-AL) buried in a Pbody, with an N+ region near the cathode separated from the MOS structure. When a gate voltage is applied, the channel generated by the MOS transfers the potential of the N-drift region to the N-AL. The highly doped N-AL experiences avalanche due to the electric field peak, and the generated electron-hole pairs serve as the base current of the thyristor, enabling the AT-MCT to rapidly establish a self-feedback mechanism. Meanwhile, the positive feedback process established by the avalanche significantly improves the two-dimensional transient carrier transport effect, increases the effective conduction area of the cell during transient turn-on, and thus achieves more efficient energy conversion. The AT-MCT exhibits a 40% increase in current peak and a 31% increase in di/dt capability compared to Cathode-Shorted MCT(CS-MCT). Moreover, by designing the doping concentration of the N-AL, non-activation protection in the non-operating state can be realized, thereby enhancing the reliability of the pulsed power system.
A novel Avalanche Triggered MOS-Controlled Thyristor(AT-MCT) is proposed, which achieves high current peak, high current rise capability (di/dt), and non-activation protection in the non-operating state during capacitor pulse discharge. The device incorporates a highly doped N Avalanche Layer(N-AL) buried in a Pbody, with an N+ region near the cathode separated from the MOS structure. When a gate voltage is applied, the channel generated by the MOS transfers the potential of the N-drift region to the N-AL. The highly doped N-AL experiences avalanche due to the electric field peak, and the generated electron-hole pairs serve as the base current of the thyristor, enabling the AT-MCT to rapidly establish a self-feedback mechanism. Meanwhile, the positive feedback process established by the avalanche significantly improves the two-dimensional transient carrier transport effect, increases the effective conduction area of the cell during transient turn-on, and thus achieves more efficient energy conversion. The AT-MCT exhibits a 40% increase in current peak and a 31% increase in di/dt capability compared to Cathode-Shorted MCT(CS-MCT). Moreover, by designing the doping concentration of the N-AL, non-activation protection in the non-operating state can be realized, thereby enhancing the reliability of the pulsed power system.
