Finite Impulse Response(FIR) is an important component in Synthetic Aperture Radar (SAR) signal processing system. Considering both of the resource and performance impact for system, based on FPGA(Field Programmable Gate Array), a SAR signal processing FIR is designed with width and order of filter configurable. By comparing DA(Distributed Arithmetic) architectures with the meaningful address width of ROM(Read Only Memory) and different input parallelism, and analyzing the throughput-resource ratio of different architectures, the best high parallelism DA architecture is obtained. Experimental results show that throughput-resource ratio is best when address width of ROM is 4 or 5; and the throughput-resource ratio increases when input parallelism increases, and when input parallelism equals to input data width, throughput-resource ratio is improved by 24%-117%. Compared to traditional fully parallel architecture, fully serial architecture and DA architecture, optimized DA architecture can improve the throughput-resource ratio by 3 110%, 76% and 86%, respectively.