A static timing analysis algorithm is proposed, which applies the delay collocation table, to reduce the relative error of critical path delay in Field Programmable Gate Array(FPGA). Based on the collocation table model of the logic element delay and interconnect delay, the algorithm takes into account the process corner variation's effect on delay parameters. In timing analysis phase, by computing the clock relationship between source node and sink node, path searching and delay calculating in multi-clock domains are achieved. Experimental results demonstrate that the relative error of critical path delay is reduced by 8.58% and 6.32% respectively on average when compared with the Program Evaluation and Review Technique(PERT) and the VTR algorithm, while the run time is only increased by 19.96% and 9.59% respectively on average.