Hardware architecture of processor based on FPGA+DSP structure
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    Abstract:

    A hardware architecture of processor based on Field Programmable Gate Array(FPGA)+ Digital Signal Processor(DSP) structure is proposed. In order to solve the problem of large amount of computation and long time in most real-time processing of Synthetic Aperture Radar(SAR) algorithm, a new hardware solution based on multi-core DSP and Serial Rapid I/O (SRIO) is proposed. Since multi-core DSP makes the processing speed in the chip faster and SRIO makes the data transmission between chips faster, this paper mainly discusses the main flow of implementing SAR algorithm by using multi-core DSP and SRIO based on FPGA+DSP architecture and optimizing the Fast Fourier Transform(FFT) algorithm by using pipeline technology in multi-core DSP. By using multi-core DSP, pipeline technology and SRIO technology, the data operation and transmission rate are faster, and the goal of shortening the calculation time is achieved.

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王占超,张耀天.一种基于FPGA+DSP的处理机硬件架构[J]. Journal of Terahertz Science and Electronic Information Technology ,2018,16(5):902~906

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History
  • Received:January 23,2017
  • Revised:February 22,2017
  • Adopted:
  • Online: November 08,2018
  • Published: