A low jitter clock shaping scheme is proposed, which solves the problem of high pulse with narrow width(less than 2 ns) and large noise floor of the reference clock source. The technical specifications achieved are the high reference clock pulse width greater than 3 ns, phase-locked phase jitter Root Mean Square(RMS) less than 5 ps after Phase Locked Loop(PLL). And the signal integrity simulation design verification is further realized through the Input/Output Buffer Information Specification (IBIS) model. At present, the scheme has been successfully used in online experiment of XG-III laser device and is in good condition. It is of great reference to the accurate implementation of the synchronization system of radiation sources in different frequency bands.