A floating-point Digital Signal Processor(DSP) hardcore structure is proposed. The hardcore structure not only is compatible with fixed-point operation, but also provides better support for floating-point operation. At present, the major manufacturers of Field-Programmable Gate Array(FPGA) use soft core to implement floating-point arithmetic, which maps floating-point arithmetic to the chip and realizes it through logical resources and DSP module. Compared with traditional methods, the proposed hard-core architecture can complete floating-point arithmetic only by using DSP module without occupying other logic resources in the FPGA. At the same time, in the design process of the DSP, the influence of load and time delay is fully considered, and the multi-level pipeline is reasonably inserted, which greatly improves the calculation efficiency of floating-point number. The floating-point DSP hard-core structure is designed and completed by the Semiconductor Manufacturing International(MCI) 28 nm technology. The simulation results of the proposed hard-core structure show that the single floating-point efficiency of addition and multiplication is 0.4 Gflops.